Aims The use of intrauterine devices (IUDs) has been one of the most effective, the safest and cost-effective methods for preventing pregnancy, for a long time. However, some complications have been reported for IUDs. The complications may be reduced by using a specific Technique for placement of IUD. The objective of this study was to introduce the rotating withdrawal Technique for the first time, which was investigated to reduce the complications of IUD insertion. Materials & Methods This historical cohort study was conducted on 1199 females who referred to Sarem Medical Center for IUD insertion from 1984 to 1995. After primary examinations, IUD was inserted by rotating withdrawal Technique. The subjects were followed up for 2 years. Findings Displacement was observed just in 20 cases (1. 67%). All of them were seen in the first month after placement. For these cases, IUD insertion was done again. After the second replacement, displacement was observed in 4 cases (0. 035%) after one month. Therefore, it was recommended to them to use another preventive method. There was no pregnancy or displacement in the other cases during 2 years. Conclusion The rotating withdrawal Technique can minimize the pregnancy rate when IUD is used. In addition to the type and quality of IUD, insertion method of IUD can increase its effectiveness.

Interleaving is a widely used Technique to overcome the burst error in systems featuring error correction. In a noncooperative environment such as satellite signal in which receiver is not aware of the structure of transmitter, interleaver should be identified, otherwise it would be impossible to identify the residual components and completing the hearing process. In satellite systems, it is a common practice to use a combinatory coding block, including reedsolomon codes and an interleaver with convolutional codes. This research presumes that convolutional code is identified and an algorithm is suggested for recognition of interleaver. In this algorithm, based on the presence of reedsolomon code, Interleaving period is identified, non-binary field degree is calculated, and a factor meeting the length of reed-solomon code would be the interleaver depth. Comparing with other available methods, in our suggested algorithm, computational complexity are reduced to O(n2) and simultaneity and accuracy of identification is higher.Additionally, Based on the simulations performed, the var (j0(k)) in order to identify the depth of Interleaver and  Æ have been used in order to synchronization.

In this paper, a new method for extending and relaxing the noise-coupling (NC) Technique is proposed to enhance the noise-shaping order without adding the number of integrators. The noise-shaping order of the introduced ∑∆ modulator whit applying a second-order noise-coupling Technique is enhanced and its performance with optimizing the noise transfer function (NTF) zeros is improved. Also, by removing the analog adder at feedforward path and transferring it to a new feedback branch before the last integrator and adding second-order NC path can be decreased the input voltage swing to the quantizer. Thus, by improving the modulator resolution, power consumption can be reduced. Mathematical analyses and behavioural simulation results confirm the effectiveness of the new NC method. To examine its performance, a 2nd-order single loop ΣΔ modulator was designed. The new noise-coupling method is used to achieve the three-order noise shaping to increase the resolution with low complexity and low-power. The results show an outstanding improvement in signal-to-noise and distortion ratio (SNDR) compared to the conventional structure.

Renewable energy, such as solar, is crucial to combating the environmental effects of fossil fuels. Some studies have proposed a step-up converter based on a conventional boost converter and a coupled inductor. This paper proposes a high step-up DC-DC converter designed for solar system applications. The Interleaving method is used at the converter's input to reduce the input current ripple and increase the voltage gain. This converter has a high voltage gain and a low voltage stress on the semiconductor elements, while the conduction losses of the converter are reduced. The proposed converter with a power of 220 watts, an input voltage of 10 volts, and an output voltage of 120 volts is simulated in MATLAB software. Ultimately, the performance of the converter has been assessed through analysis and simulation. Furthermore, the converter's performance was compared with several similar topologies. The results and comparisons clearly demonstrate the effectiveness of the proposed converter.

This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit Interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature decreases write mode failure. An access buffer seperates storage node from read access transistor to improve cell stability and prevent data-related leakage in read operation. Applying virtual ground also reduces the leakage. Furthermore, we design the cell control unit. The simulation results at VDD=0. 5V exhibit the effectiveness of our proposed cell compared with other counterparts which are suitable for bit Interleaving structure. Comparison results on the proposed cell and 6T cell show our cell improved 70% in write power consumption and 90. 45% in read power consumption.

High gain Balun-low-noise-amplifier (LNA) is proposed for tuner of digital televisions (DTVs). The proposed Balun-LNA is based on CS-CG (common-source-common-gate) structure. To improve the isolasion and frequency response, Balun-LNA has cascode transistors before load resistors. Balun-LNA uses current-bleeding circuit to increasie transconductance of CS transistor, so that current-bleeding transistor has transconductance of N-1 times larger than transconductance of cascode transistor. Thereby, transconductance and current of CS transistor are increased N times, as N-1 times of current pass to current-bleeding transistor. Therefore current of CG and CS stages stay identical. Also, Balun-LNA employs a positive feedback to satisfy input impedance matching and CG transistor has higher transconductance. By increasing transconductance of CS and CG transistors, the proposed Balun-LNA achieves to high voltage gain. Accordingly, CG and CS tansistors have symmetrical currents and loads at the differential output of the proposed Balun-LNA. Symmetrical loads cause the balanced differential outputs. This proposed Balun-LNA is designed in 90-nm CMOS technology and covers the frequency range of 40 MHz to 1GHz. This Balun-LNA achieves the voltage gain of 22.6 dB, S11 of less than -10 dB and the Minimum NF of 5 dB. This Balun-LNA operates at the nominal supply voltage of 2.2v.

In this paper, a 8T SRAM cell in sub-threshold region is presented which in addition to read and write operation improvements, reduces power consumption significantly. The proposed cell carries out write operation differentially and has a single ended read operation. In this design, using an appropriate combination of Techniques, leads to improvements the cell performance. These methods include weakening feedback in the write mode, applying the boosted word line, eliminating one of the driver transistors and isolating storage node from access transistor by a buffer. The simulation results at 32 nm PTM technology and VDD 0. 3 V show the proposed cell improves read and write power consumption 93%and 80%, respectively compared with 6T cell. Moreover, the proposed cell has lower power consumption and stronger write mode compared with other bit Interleaving cells. Furthermore, the proposed cell has a desired performance in the read mode.

In this paper, a novel LNA design based on improved noise cancellation Technique in the frequency range of 27 to 31 GHz.is presented The proposed LNA is suitable for millimeter wave 5G wireless communication. The first stage of this two-stage LNA is designed with noise cancelation approach to decrease the noise figure of the system. In order to improve the design method, we utilizes a negative feedback by implementing a couple inductor with a transformer connection. The negative feedback provides an acceptable input matching and control the gain to increase the band width. The cascode structure is used in the second stage for its higher gain and stability and better reverse isolation at millimeter wave frequency. Furthermore, an inductor is utilized to boost the gain with neutralizing the capacitance of node between two transistors in a cascode structure. The CMOS silicon on insulator (SOI) is utilized to provide a high level of integration and low power consumption with the minimum cost. The proposed LNA is designed with 130 nm CMOS technology and has 22.14 dB gain with 1.86 dB noise figure at 29 GHz. The 3-dB bandwidth of the designed LNA is 4 GHz (14%) and its DC power consumption is 33.4 mW. The IIP3 is -16dBm and input reflection coefficient is better than -10dBm in the frequency range of interest. The proposed LNA is simulated by ADS software.